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arXiv cs.AI· Borui Xu, Hongshi Tan, Wenqi Jiang, Bingsheng He, Ming Wu, Jason Zeng, Michael Heinrich·· 3 小时前AI 评分47

VLA-HWBench:VLA 模型在边缘硬件上运行时时间去哪了

VLA-HWBench: Where the Time Goes When VLA Models Run on Edge Hardware

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VLA-HWBench 在 NVIDIA Jetson AGX Thor 和 AMD Ryzen AI Max+ PRO 395 上对 18 个开源 VLA 模型进行七阶段推理拆解。

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Abstract:Vision--language--action (VLA) models increasingly run on edge devices aboard robots, where inference latency constrains closed-loop robot control. However, it remains unclear how to design VLA models, their inference software and edge hardware so that robots can run VLA inference in real time. Most VLA models report only task success, while prior studies cover limited action-generation strategies, divide inference into at most three stages, and lack comparisons of inference optimizations on the same this http URL 18 open VLA models across released and alternative backends on NVIDIA Jetson AGX Thor and AMD Ryzen AI Max+ PRO 395, with a seven-stage inference breakdown. Our study reveals three insights. First, action-generation strategy matters more than model size. It dominates 14 of 19 Jetson configurations, latency varies by $82\times$ on Jetson and $157\times$ on AMD, and parameter count explains at most 15% of latency variance. Models that generate long action chunks in a few flow-matching steps keep up with control, whereas token-by-token decoding does not. Second, kernel fusion with 4-bit weights helps most, running $\pi_{0.5}$ and GR00T N1.7 2.6--2.9$\times$ faster than PyTorch with \texttt{this http URL}, but it exists for only these two models and only on the Jetson. Optimization also moves the time to the stages it shortens least, as CPU preprocessing grows from 12\% to 39\% of the GR00T N1.7 call. Third, after optimization, memory bandwidth limits only the stages that process few tokens on the Jetson, such as the denoising steps, whereas software limits all other stages, from unfused kernels to serial preprocessing on the host CPU. Overall, low-latency edge VLAs should use few action-generation iterations, inference software should extend kernel fusion and low-bit weights to more models and platforms, and edge hardware needs high memory bandwidth and a fast host CPU.
Subjects: Robotics (cs.RO); Artificial Intelligence (cs.AI)
Cite as: arXiv:2610.34717 [cs.RO]
  (or arXiv:2610.34717v1 [cs.RO] for this version)
  https://doi.org/10.48550/arXiv.2610.34717

arXiv-issued DOI via DataCite (pending registration)

Submission history

From: Borui Xu [view email]
[v1] Mon, 26 Oct 2026 02:07:42 UTC (484 KB)

来源:arXiv cs.AI · arxiv.org