ICLayout-Bench：评测 LLM 智能体定制电路版图设计的基准

Authors:Zhangmai Li, Tianrui Ma, Zheng Weng, Mo Zou, Zidong Du, Yifan Hao, Yongwei Zhao, Wei Li, Jing Li, Qi Guo, Yunji Chen

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Abstract:Large language model (LLM) agents are being explored for circuit design, but their ability to produce high-quality custom layouts has not been extensively evaluated. ICLayout-Bench is a benchmark in which agents use electronic design automation (EDA) tools to construct and optimize GDSII layouts from transistor-level circuit netlists. These layouts are evaluated using physical verification, parasitic extraction, and post-layout simulation. Layouts that pass the physical and functional checks are scored on electrical performance and area. The benchmark includes 165 tasks across 13 process design kits (PDKs), covering technology nodes from 3 nm to 180 nm. The tasks span analog, mixed-signal, and digital circuits in open-source and commercial EDA flows. The experiments evaluate 22 configurations spanning seven models on 21 public and 19 private tasks. Mean layout scores range from 4.22 to 80.26 on public tasks and from 1.43 to 67.01 on private tasks, on a 100-point scale. Higher reasoning effort does not consistently improve mean scores, and configurations with comparable scores can incur substantially different model costs.

Comments:	12 pages, 7 figures, 3 tables, including appendices. Project page: this https URL Code: this https URL Dataset: this https URL
Subjects:	Hardware Architecture (cs.AR); Artificial Intelligence (cs.AI); Software Engineering (cs.SE)
Cite as:	arXiv:2611.12982 [cs.AR]
	(or arXiv:2611.12982v1 [cs.AR] for this version)
	https://doi.org/10.48550/arXiv.2611.12982 arXiv-issued DOI via DataCite (pending registration)

Submission history

From: Zhangmai Li [view email]
[v1] Sun, 8 Nov 2026 08:05:27 UTC (396 KB)