从自然语言到真实原理图：电力电子原理图自动合成工作流
From Natural Language to Real Schematics: An Automated Workflow for Power Electronics Schematic Synthesis
AI 导读
一项 arXiv 论文提出有界双环自动原理图合成框架，将自然语言规格转化为可验证、可编辑的 KiCad 原理图，覆盖 Buck、Boost、Flyback、DAB、半桥 LLC 拓扑，并结合分销商 API、OEM 数据手册选型与 ngspice 瞬态闭环验证。
正文 · 原文
Abstract:Designing power electronics converters traditionally requires intensive human expertise across topology sizing, commercial component selection, circuit simulation verification, and schematic drafting. While Large Language Models (LLMs) show promise in electronic design automation (EDA), applying standalone LLMs directly to board-level power electronics schematic synthesis suffers from severe engineering hallucinations, including inaccurate analytical sizing, fabricated or mismatched component part numbers, violated voltage derating margins, and broken topological connectivity. In this paper, we propose a Bounded Dual-Loop Automated Schematic Synthesis Framework that translates natural language specifications into verified, editable KiCad schematics and manufacturing deliverables. Our workflow integrates six stages across three functional columns: (1) requirement parsing and knowledge-driven power stage synthesis covering non-isolated (Buck, Boost) and isolated/resonant (Flyback, DAB, half-bridge LLC) topologies; (2) contract- and evidence-coordinated component selection grounded in distributor APIs and OEM datasheets, coupled with closed-loop ngspice transient verification and stress feedback; and (3) modular control hardware integration and multi-format deliverable generation featuring native KiCad netlist round-trip verification. End-to-end case studies on a 24-36V to 12V,2A Buck converter (29 positions, 83 verified terminals) and an isolated 48V to 24V, 0.5A, Dual-Active Bridge (DAB) converter (87 positions, 341 verified terminals), alongside comparative evaluations against a Vanilla LLM baseline, demonstrate that our framework improves component verification coverage from 22.2 to 98.6, nominal value consistency from 0 to 97.7, and SPICE simulation pass rates from 0 to 100.
| Subjects: | Artificial Intelligence (cs.AI) |
| Cite as: | arXiv:2610.38201 [cs.AI] |
| (or arXiv:2610.38201v1 [cs.AI] for this version) | |
| https://doi.org/10.48550/arXiv.2610.38201 arXiv-issued DOI via DataCite |
Submission history
From: Bowen Su [view email]
[v1]
Wed, 28 Oct 2026 02:52:01 UTC (4,505 KB)
来源：arXiv cs.AI · arxiv.org