BTTF：面向芯片设计验证智能体系统的 EDA 基础设施重构
Back to the Future: Rethinking EDA Infrastructure for Agentic Systems in Chip Design Verification
AI 导读
arXiv 论文提出 Back-to-the-Future（BTTF），一个端到端智能体框架，填补现有 EDA 研究多集中于静态 RTL 代码生成（约 74.6%）而缺乏后仿真验证的空白。
正文 · 原文
Abstract:The unprecedented computational scale of modern artificial intelligence depends on complex, multi-billion-transistor Systems-on-Chip, yet the workflows that verify these chips remain stubbornly manual. Although Large Language Models (LLMs) have made rapid inroads into Electronic Design Automation (EDA), approximately 74.6% of existing studies target static Register-Transfer Level (RTL) code generation, leaving post-simulation verification and interactive waveform debugging largely untouched. We introduce Back-to-the-Future (BTTF), an end-to-end agentic framework that closes this infrastructural gap. BTTF distills massive, unstructured simulation dumps into a normalized relational SQLite database and couples it with a collaborative multi-agent orchestration engine that translates natural-language verification queries into schema-aware SQL while correlating signal anomalies with versioned RTL repositories. Across a 150-query benchmark, BTTF attains 95.33% execution accuracy, charting a practical path toward autonomous EDA verification.
| Comments: | 40th NeurIPS'26 Workshop AI for Chip Design |
| Subjects: | Artificial Intelligence (cs.AI) |
| Cite as: | arXiv:2610.06790 [cs.AI] |
| (or arXiv:2610.06790v2 [cs.AI] for this version) | |
| https://doi.org/10.48550/arXiv.2610.06790 arXiv-issued DOI via DataCite |
Submission history
From: Je Yang [view email]
[v1]
Mon, 5 Oct 2026 17:48:14 UTC (394 KB)
[v2]
Thu, 22 Oct 2026 20:12:37 UTC (394 KB)
来源：arXiv cs.AI · arxiv.org