AnalogPortBench：评测大语言模型在模拟电路工艺移植上的基准
AnalogPortBench: Benchmarking LLMs on Analog Circuit Porting
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研究者发布 AnalogPortBench，这是一个评测 LLM 模拟电路工艺移植能力的基准，包含 54 个任务，涉及将 10 种电路（从电流镜到望远镜放大器）从 0.18 μm 工艺移植到开源 SKY130 PDK。
正文 · 原文
Abstract:Analog circuit design still relies heavily on expert knowledge, and porting proven designs to new process nodes is a recurring bottleneck. As a lower supply reduces available voltage headroom, a working topology may require redesign or fail to meet specifications. While large language models (LLMs) have begun to generate and optimize analog circuits, existing benchmarks focus on one process node and assume feasible specifications. To bridge this gap, we introduce AnalogPortBench, a benchmark of 54 tasks for porting ten circuits, from current mirrors to telescopic amplifiers, from a 0.18 $\mu$m process to the open-source SKY130 PDK. Tasks range from a direct port through a reduced supply and harder specifications to infeasible ones, and every feasible task has a reference design verified at five process corners. Evaluating six frontier LLMs at two reasoning levels, with and without simulation feedback, we find that models port simple circuits but rarely re-design headroom-sensitive amplifiers, seldom recognize infeasible specifications, and gain more from simulation feedback than from more samples or reasoning. Code and data are available at this https URL.
| Comments: | 5 pages, 3 figures, 4 tables Code and data: this https URL |
| Subjects: | Hardware Architecture (cs.AR); Artificial Intelligence (cs.AI) |
| Cite as: | arXiv:2610.33088 [cs.AR] |
| (or arXiv:2610.33088v1 [cs.AR] for this version) | |
| https://doi.org/10.48550/arXiv.2610.33088 arXiv-issued DOI via DataCite |
Submission history
From: Saeid Rajabi [view email]
[v1]
Wed, 21 Oct 2026 20:45:51 UTC (275 KB)
来源：arXiv cs.AI · arxiv.org