DEX：数字级早退的 MSDF 节能神经网络推理论文被作者撤回
DEX: Digit-Level Early Exit for Energy-Efficient MSDF Neural Network Inference
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论文《DEX: Digit-Level Early Exit for Energy-Efficient MSDF Neural Network Inference》（arXiv:2610.11748）已由第一作者 Muhammad Usman 撤回，原因是缺少最终合著者批准，并将更新方法、补充更多结果。
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This paper has been withdrawn by Muhammad Usman
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Abstract:U-Net inference for brain-tumor segmentation requires billions of multiply-accumulate operations, motivating hardware that can reduce computation dynamically rather than relying only on fixed precision or static model compression. Most-significant-digit-first (MSDF) arithmetic exposes the leading digits of a result during computation, enabling output-dependent decisions before the full value is generated. This paper presents an MSDF accelerator for quantized U-Net segmentation with a two-stage grouped processing element supporting signed INT8 operands and in-stream bias accumulation. Four runtime mechanisms operate directly on the output digit stream: exact early negative detection (END) in ReLU layers, exact sign-only decision making in the segmentation head, calibrated low-order-digit skipping, and calibrated pruning. The two approximate mechanisms are selected offline under an accuracy constraint, while execution requires only lightweight control and does not modify the stored weights. On a residual U-Net trained with nnU-Net for BraTS, the proposed mechanisms reduce digit cycles by 38.38\% while achieving a mean Dice score of 80.58\% on 73 held-out cases, compared with 81.20\% for the floating-point model; the exact mechanisms alone reduce cycles by 18.79\% without altering the quantized output. Synthesized in 45~nm, the processing element operates at 500~MHz, occupies 0.858~mm$^2$, and consumes 0.726~mJ per $192\times192$ patch under switching-activity-annotated power analysis. A projected eight-output accelerator with shared activation delivery achieves 16.6~ms latency and 1.67~mJ per patch.
| Comments: | Withdrawn by the authors due to missing final co-author approval, and to allow for updates to the methodology and the inclusion of further results |
| Subjects: | Hardware Architecture (cs.AR); Artificial Intelligence (cs.AI); Machine Learning (cs.LG) |
| Cite as: | arXiv:2610.11748 [cs.AR] |
| (or arXiv:2610.11748v2 [cs.AR] for this version) | |
| https://doi.org/10.48550/arXiv.2610.11748 arXiv-issued DOI via DataCite |
Submission history
From: Muhammad Usman [view email]
[v1]
Thu, 8 Oct 2026 11:39:01 UTC (3,477 KB)
[v2]
Thu, 29 Oct 2026 22:05:11 UTC (1 KB) (withdrawn)
来源：arXiv cs.AI · arxiv.org